Embodiments of the present disclosure relate to a decoding circuit, and more particularly to a technology for changing a decoding structure without changing a circuit structure.
In a semiconductor circuit configured to process digital data, certain data is represented by a binary code. The binary code composed of N bits may represent a maximum of 2N coded information elements. A decoding circuit is a combination circuit configured to convert binary information in such a manner that N coded input data signals are converted into a maximum of 2N decoded output data signals, wherein N is a positive integer.
In addition, a coded address is used to select a specific cell from a semiconductor memory device. Therefore, when data is recorded in a specific cell of the semiconductor memory device or data is read from the specific cell, an address decoding process is needed. To perform the address decoding process, the semiconductor memory device generally includes a row decoder and a column decoder.
For example, it is assumed that there is a decoding circuit for outputting 8 output signals OUT<7:0> by decoding 3 input signals IN<2:0>.
If an input signal IN is set to “000,” the decoding circuit outputs the output signal OUT as “00000001.” If the input signal IN is set to “001,” the decoding circuit outputs the output signal OUT as “00000010.” If the input signal IN is set to “010,” the decoding circuit outputs the output signal OUT as “00000100.” In addition, if the input signal IN is set to “011,” the decoding circuit outputs the output signal OUT as “00001000.”
If the input signal IN is set to “100,” the decoding circuit outputs the output signal OUT as “00010000.” If the input signal IN is set to “101,” the decoding circuit outputs the output signal OUT as “00100000.” If the input signal IN is set to “110,” the decoding circuit outputs the output signal OUT as “01000000.” If the input signal IN is set to “111,” the decoding circuit outputs the output signal OUT as “10000000.”
When the decoding circuit is configured to output 8 output signals by decoding 3 input signals, the decoding circuit generates binary information of the output signal OUT mandatorily including a code “1.”
Subsequently, it is assumed that there is a decoding circuit that outputs 6 output signals OUT<5:0> by decoding 3 input signals IN<2:0>.
If the input signal IN is set to “000,” the decoding circuit outputs the output signal OUT as “00000001.” If the input signal IN is set to “001,” the decoding circuit outputs the output signal OUT as “00000010.” If the input signal IN is set to “010,” the decoding circuit outputs the output signal OUT as “00000100.” If the input signal IN is set to “011,” the decoding circuit outputs the output signal OUT as “00001000.”
If the input signal IN is set to “100,” the decoding circuit outputs the output signal OUT as “00010000.” If the input signal IN is set to “101,” the decoding circuit outputs the output signal OUT as “00100000.”
If the input signal IN is set to “110,” the decoding circuit outputs the output signal OUT as “00000000,” resulting in implementation of a “Don't care” state. If the input signal IN is set to “111,” the decoding circuit outputs the output signal OUT as “00000000,” resulting in implementation of a “Don't care” state.
The “Don't care” state in which binary information of the output signal OUT does not include the code “1” may occur in the decoding circuit configured to output 6 output signals by decoding 3 input signals.
As described above, if the number of bits of the output signal OUT is changed, there is a need to change a circuit structure of the decoding circuit. However, after the circuit structure of the decoding circuit is decided, it is difficult to change the circuit structure of the decoding circuit. In addition, if the number of bits of the output signal OUT is increased, the decoding circuit is unavoidably increased in size.